I. Field of the Invention
The present invention relates generally to logic in computers and, more particularly, to a system and method for clocking pipelined stages of self-timed dynamic logic gates, also known as "mousetrap" logic gates.
II. Related Art
Pipelining in computer logic generally refers to the concept of configuring various stages of logic in sequence, whereby data is initially introduced into the sequence of logic stages and then subsequently more data is introduced before completion of the operation on the first data through the sequence. Pipelining enhances the performance of high "latency" logic networks. High latency logic networks are logic circuits which perform long sequences of logic operations requiring a relatively large amount of time. Pipelining improves performance because pipelining permits the overlapping of operation execution.
At present, pipelining is considered a requirement for high latency logic networks in the high performance arena. For instance, instruction execution logic in the central processing unit (CPU) of a computer invariably employ pipelining.
As a further example of where pipelining is considered a necessity, consider multiplication. To perform multiplication, a "carry save adder" pipeline of logic stages is usually employed. Specifically, each pipeline stage is essentially several rows of conventional full adder logic stages. Moreover, each full adder compresses three partial products into two partial products. Thus, each full adder adds in another partial product as data flows through the chain of full adder logic stages in each pipeline stage. In order to perform a single multiplication operation, more than one clock cycle is usually required, but as a result of pipelining, a new multiplication operation may be commenced generally in substantially less than, perhaps in half of, the total number of clock cycles.
Traditionally, "static" logic gates have been utilized in computers to perform logic functions, for example, mathematical operations. Static logic gates are those which can continuously perform logic operations so long as electrical power is available. In other words, static logic gates need no electrical precharge, or refresh, in order to properly perform logic operations. Static logic gates can be easily connected together in sequence to collectively perform logic functions in an efficient manner.
However, static logic gates are slow individually. In addition, when static logic gates are pipelined, the resulting logic operation is performed in an even slower manner.
"Dynamic" logic gates are also known in the art. Dynamic logic gates are used in the conventional design of logic circuits which require high performance and modest size. Dynamic logic gates are much faster than static logic gates. However, dynamic logic gates require a periodic electrical precharge, or refresh, such as with a dynamic random access memory (DRAM), in order to maintain and properly perform their intended logic function. Once an electrical precharge supplied to a dynamic logic gate has been discharged by the dynamic logic gate, the dynamic logic gate can no longer perform another logic function until subsequently precharged.
However, the use of conventional dynamic logic circuits in combinational logic or pipelining is problematic. First, dynamic logic circuits require a precharge cycle in order to render them operative. Effectively, a precharge cycle periodically interrupts the useful work cycle for the necessary purpose of maintenance. Precharge cycles significantly and undesirably increase the execution time of a sequence of logic stages.
Dynamic logic circuits must maintain a minimum clock frequency in order to insure proper functioning. Proper operation of dynamic logic circuits requires that an electrical charge be deposited and maintained in the circuits. In reality, the charge deposited in the logic circuits eventually will decay to an unknown logic level and thereby corrupt the state of the pipeline. The decay results from uncontrollable design and manufacture characteristics. In most practical situations, the preceding problem may be overcome via a periodic refresh cycle, similar to the refresh cycle in conventional dynamic random access memory (DRAM). Hence, a minimum clock rate, analogous to refresh cycles, must be maintained.
However, the minimum clock rate poses an additional problem. Many times, logic circuits are required to operate arbitrarily slow, "at DC." For instance, logic circuits may be required to operate slow during IC testing. Conventionally, dynamic logic circuits can be modified to exhibit slow operation by including "trickle charge" devices or "cross-coupled negative feedback" devices. However, these devices consume valuable computer real estate and further decrease the speed of the logic circuits.
Thus, a need exists in the industry for teachings that will permit the high performance pipelining of dynamic logic circuitry which adequately preserves data without the need for a minimum (refresh) clock rate.